搜索资源列表
Multiplier4X4
- 乘法器:4bit*4bit,兩個輸入,一個輸出,這個是verilog程式,名字是Multiplier4X4,功能是乘法。-Multiplier: 4-bit* 4bit, two inputs, one input, this is a verilog program name Multiplier4X4, function is multiplication.
CAM
- 本文档是基于ISE的verilog编程,描述的是一个用CAM方法编的一个乘法器,是四位乘以四位的乘法器。-This document is based on the ISE verilog programming described a CAM method to a series of multipliers, the multipliers of four multiplied by four.
16-parallel-multiplier
- 简单16位并行乘法器的Verilog程序-16 parallel multiplier Verilog program
mult_16
- 用verilog实现对三个16位数进行相加乘法器-Three 16-digit sum of the multiplier Verilog
16mult_signed
- 16*16位的有符号乘法器的verilog语言-16 x 16 signed multiplier verilog language
mulx
- FPGA verilog乘法器 设计 用FPGA中DSP模块实现-FPGA verilog mulx
chengfaqi
- verilog语言编写的一个乘法器程序,是16位相乘!已通过仿真,用Quartus II 9.1 编写-a multiplier verilog language program, is 16 multiplied by! Through simulation, the Quartus II 9.1 to write
Multiplier16
- 本文设计了一种可以实现16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了补码一位乘(Booth算法), 简化了部分积的数目, 减少了某些加法运算,从而提高了运算速度。该乘法器利用Verilog代码实现,通过Modelsim软件对相应的波形进行仿真验证,并通过QuartusII软件对源码进行编译综合。-This paper designed a 16 signed/unsigned binary number multiplication of the multiplier can be a
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
develop_frame_find
- 基于FPGA中OFDM中的帧检测,由于采用简化算法,采用较少的复数乘法器,易于硬件实现,且节省资源,采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower th
Multiplier
- 圖形介面乘法器,也可自行使用verilog去改-Graphical interface multiplier, also free to use verilog go and change
mux16
- 乘法器,verilog语言实现,16位*16位,位数可调,改动相应程序即可。-Multiplier, verilog language to achieve, 16* 16 digit adjustable changes corresponding program can.
work
- 这里面包含了从易到难的6个很经典的verilog例子,有序列检测器,3位乘法器,数字报表等-It contains from easy to difficult six very classic verilog example, a sequence detector, three multiplier, digital statements, and so on
MULT
- 用VERILOG实现乘法器功能,通过仿真验证-With VERILOG multiplier function is verified by simulation
lbq3
- 滤波器的verilog代码 主要是对算法的折叠 有原先的4个加法器四个乘法器变成2个加法器两个乘法器-Filter verilog code folding algorithm 4 adder four multipliers into two adders and two multipliers
Multiplier
- 详细介绍了给予Verilog的乘法器设计过程。-Details the the multiplier given Verilog design process.
mux16
- 16位乘法器的verilog实现,可以通过仿真,采用的是移位的方法。-16-bit multiplier verilog achieve, through simulation, using the shift method.
Mul32
- Verilog语言编写的单精度浮点数乘法器-The Verilog language of single precision floating point multiplier
costasc_verilog
- 实现costas环,用verilog语言实现,缺少乘法器,可以自己添加-Realization of Costas ring, with the Verilog language implementation, the lack of multiplier, you can add their own.
RS_dec
- rs(204,188)译码器,verilog实现,乘法器采用比特异或方式实现-rs (204,188) decoder, verilog achieve multiplier used than specific or way